The present invention relates generally to large-scale integration and more specifically to an LSI chip having a test circuit that enables the determination of the dynamic performance of the chip through activated logical paths at chip's operating speed.
According to one prior art LSI chip which is shown in FIG. 1, a combinational logic circuit 1 has a plurality of inputs which are divided into two groups 2a and 2b and a plurality of outputs similarly divided into groups 3a and 3b. Data are supplied through inputs 2a and delivered through outputs 3a. Outputs 3b are respectively coupled to switching gates 4 whose outputs are in turn coupled respectively to data inputs of successively arranged flip-flops 5-1 through 5-n. The outputs of the flip-flops are respectively coupled to inputs 2b on the one hand and to an input of the next switching gate 4 except for flip-flop 5-n whose output is coupled to a scan-out terminal SO. During a normal mode, a logic 0 is applied to a scan-control terminal SC to permit data from outputs 3b to be passed to the associated flip-flops so that the flip-flops 5-1 through 5-n form part of a sequential logic circuit with the combinational logic circuit 1. During a test mode, scan (test) data is applied to a scan-in terminal SI and a logic 1 is applied to scan-control terminal SC to cause the scan data to be sequentially shifted from one flip-flop to the next in a similar fashion to a shift register and a series of scan data are loaded into the flip-flops for coupling to inputs 2b of the logic circuit. Subsequently, a logic 0 is applied to the scan control terminal SC to deliver output data through outputs 3b to the associated flip-flops through switching gates 4 and the flip-flops are clocked to store the output data. Finally, a logic 1 is applied to the scan control terminal SC to sequentially read the stored test data from the scan-out terminal SO. Although satisfactory for generating test data for measurement of the static performance of a desired logical path, this "scan path" approach is incapable of generating such test data which allows measurement of propagation delays or dynamic performance of the logic circuit along activated paths.
Another prior art, which is shown in FIG. 2, is a combination of combinational logic circuits 6, 7 in which the scan path is in the form of linear feedback shift registers 8, 9 respectively interposed between the logic circuits 6 and 7 to generate pseudo-random test data and store them in a compressed form. While this approach is capable of testing at the operating speed of the logic circuits, it is incapable of generating such test data which allows activation of desired logical paths within the logic circuits and measurement of propagation delays along the activated logical paths.